Field of the Disclosure
The present disclosure relates generally to integrated circuit devices and more particularly to on-die signal measurement and characterization.
Description of the Related Art
Variations in a semiconductor fabrication process can lead to non-identical performance between resulting integrated circuit (IC) devices. Typically, these variations are manifested in variations in the doping concentration, dimensions, and other parameters of the transistors of the IC devices, and can result in significant changes to the duty cycle, skew rate, and other timing uncertainties in signaling conducted by the transistors. To accommodate these process variations, semiconductor device manufacturers may implement an on-die digital delay line (DDL) to obtain an on-die measurement of a timing characteristic of a signal.
Typically, the DDL comprises a delay chain of inverters (or buffers) and a set of flip-flops to sample the output of each inverter of the delay chain. Decoder logic is then used to generate a digital reading from the outputs of the set of flip-flops. However, to cover all standard process corners, the number of inverter/flip-flop combinations in the DDL conventionally covers the entire spread from the slowest process corner (that is, the slow-nmos slow-pmos, or SS, process corner), to the average process corner (that is, the typical-nmos typical-pmos, or TT, process corner) to the fastest process corner (that is, the fast-nmos fast-pmos, or FF, corner). Moreover, conventional decoding logic used to decode the digital output of the DDL utilizes a flip-flop for each flip-flop used in the DDL.
In many circumstances, the total number of flip-flops needed to implement a conventional DDL and corresponding decoding logic for the contemplated process corner spread can number in the hundreds, which can be impracticable due to power-consumption, area, and accuracy considerations, particularly when multiple on-die clock measurement circuits are contemplated for a system. Moreover, DDL-based characterization circuits often require near zero-skew between the various flip-flops in order to operate accurately. Given the number of flip-flops implemented in conventional DDL-based characterization circuits, this design requirement often is difficult to meet, especially at the lower voltages often found in modern IC devices.